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64K x 32 3.3V Synchronous SRAM Flow-Through Outputs Burst Counter, Single Cycle Deselect Features
64K x 32 memory configuration Supports high performance system speed Commercial: -- 11 11ns Clock-to-Data Access (50 MHz) Commercial and Industrial: -- 12 12ns Clock-to-Data Access (50 MHz) Single-cycle deselect functionality (Compatible with Micron Part # MT58LC64K32B2LG-XX) LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) Power down controlled by ZZ input Single 3.3V power supply (+10/-5%) Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP).
IDT71V633
x x
x
x x
x x x
Description
The IDT71V633 is a 3.3V high-speed 2,097,152-bit (2-Mbit) SRAM organized as 64K x 32 with full support of various processor interfaces including the PentiumTM and PowerPCTM. The flow-through burst archi-
tecture provides cost-effective 2-1-1-1 performance for processors up to 50 MHz. The IDT71V633 SRAM contains write, data-input, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the extreme end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V633 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses will be defined by the internal burst counter and the LBO input pin. The IDT71V633 SRAM utilizes IDT's high-performance 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP).
Pin Description
A0-A15 CE CS0, CS1 OE GW BWE BW1-BW4 CLK ADV ADSC ADSP LBO ZZ I/O0-I/O31 VDD, VDDQ VSS, VSSQ Address Inputs Chip Enable Chips Selects Output Enable Global Write Enable Byte Write Enable Individual Byte Write Selects Clock Input Burst Address Advance Address Status (Cache Controller) Address Status (Processor) Linear / Interleaved Burst Order Sleep Mode Data Input/Output Core and I/O Power Supply (3.3V) Array Ground, I/O Ground Input Input Input Input Input Input Input Input Input Input Input Input Input I/O Power Power Synchronous Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Synchronous Synchronous DC Asynchronous Synchronous N/A N/A
3780 tbl 01
Pentium is a trademark of Intel Corp. PowerPC is a trademark of International Business Machines, Inc.
AUGUST 2001
1
DSC-3780/05
(c)2000 Integrated Device Technology, Inc.
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol A0-A15 ADSC Pin Function Address Inputs Address Status (Cache Controller) Address Status (Processor) Burst Address Advance I/O I I Active N/A LOW Description Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK and ADSC Low or ADSP Low and CE Low. Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the address registers with new addresses. ADSC is NOT gated by CE. Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address registers with new addresses. ADSP is gated by CE. Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter, controlling burst access after the initial address is loaded. When this input is HIGH the burst counter is not incremented; that is, there is no address advance. Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWX inputs are passed to the next stage in the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of CLK. If ADSP is HIGH and BWX is LOW at the rising edge of CLK then data will be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle. Synchronous byte write enables. BW1 controls I/O(7:0), BW2 controls I/O(15:8), etc. Any active byte write causes all outputs to be disabled. ADSP LOW disables all byte writes. BW1-BW4 must meet specified setup and hold tim es with respect to CLK. Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V633. CE also gates ADSP. This is the clock input. All timing references for the device are made with respect to this input. Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip. Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip. Synchronous global write enable. This input will write all four 8-bit data bytes when LOW on the rising edge of CLK. GW supercedes individual byte write enables. Synchronous data input/output (I/O) pins. Only the data input path is registered and triggered by the rising edge of CLK. Outputs are Flow-Through. When LBO is HIGH the Interleaved Order (Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst sequence is selected. LBO has an internal pull-up resistor. Asynchronous output enable. When OE is HIGH the I/O pins are in a high-impedence state. When OE is LOW the data output drivers are enabled if the chip is also selected. 3.3V core power supply inputs. 3.3V I/O power supply inputs. Core ground pins. I/O ground pins. NC pins are not electrically connected to the chip. Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V633 to its lowest pow er consumption level. Data retention is guaranteed in Sleep Mode. ZZ has an internal pull-down resistor.
3780 tbl 02
ADSP ADV
I I
LOW LOW
BWE
Byte Write Enable
I
LOW
BW1-BW4
Individual Byte Write Enables
I
LOW
CE CLK CS0 CS1 GW I/O0-I/O31 LBO
Chip Enable Clock Chip Select 0 Chip Select 1 Global Write Enable Data Input/Output Linear Burst
I I I I I I/O I
LOW N/A HIGH LOW LOW N/A LOW
OE
Output Enable
I
LOW
VDD VDDQ VSS VSSQ NC ZZ
Power Supply Power Supply Ground Ground No Connect Sleep Mode
N/A N/A N/A N/A N/A I
N/A N/A N/A N/A N/A HIGH
NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
2
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO ADV
CE Burst Sequence INTERNAL ADDRESS
CLK ADSC ADSP
CLK EN ADDRESS REGISTER Byte 1 Write Register
Binary Counter CLR
2
Burst Logic
16 A0* A1*
Q0 Q1
64K x 32 BIT MEMORY ARRAY
2 16
A0, A1
A0-A15 GW BWE BW1
A2-A15 32 32
Byte 1 Write Driver
Byte 2 Write Register
8
Byte 2 Write Driver
BW2
Byte 3 Write Register
8
Byte 3 Write Driver
BW3
Byte 4 Write Register
8
Byte 4 Write Driver
BW4
8
CE CS0 CS1
D Q Enable Register
DATA INPUT REGISTER
CLK EN
ZZ OE
32
Powerdown
OE OUTPUT BUFFER
.
I/O0-I/O31
3780 drw 01
3 6.42
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Absolute Maximum DC Ratings(1)
Symbol VTERM (2) VTERM TA TBIAS TSTG PT IOUT
(3)
Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Value -0.5 to +4.6 -0.5 to VDD+0.5 0 to +70 -55 to +125 -55 to +125 1.2 50
Unit V V
o o o
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0C to +70C -40C to +85C VSS 0V 0V VDD 3.3V+10/-5% 3.3V+10/-5% VDDQ 3.3V+10/-5% 3.3V+10/-5%
3780 tbl 03
C C C
W mA
3780 tbl 05
Recommended DC Operating Conditions
Symbol VDD VDDQ Parameter Core Supply Voltage I/O Supply Voltage Min. 3.135 3.135 0 2.0
(1) (3)
Typ. 3.3 3.3 0
____ ____
Max. 3.63 3.63 0 VDDQ+0.3 0.8
(2)
Unit V V V V V
3780 tbl 04
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD, VDDQ and input terminals only. 3. I/O terminals.
VSS, VSSQ Ground VIH VIL Input High Voltage Input Low Voltage
-0.5
NOTES: 1. VIH and VIL as indicated is for both input and I/O pins. 2. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle. 3. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
Capacitance
Symbol CIN CI/O
(TA = +25C, f = 1.0MHz, TQFP package)
Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 4 8 Unit pF pF
3780 tbl 06
NOTE: 1. This parameter is guaranteed by device characterization, but not production tested.
4
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration
A6 A7 CE CS0 BW4 BW3 BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC I/O16 I/O17 VDDQ VSSQ I/O18 I/O19 I/O20 I/O21 VSSQ VDDQ I/O22 I/O23 VSS(1) VDD NC VSS I/O24 I/O25 VDDQ VSSQ I/O26 I/O27 I/O28 I/O29 VSSQ VDDQ I/O30 I/O31 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67
PK100-1
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC I/O15 I/O14 VDDQ VSSQ I/O13 I/O12 I/O11 I/O10 VSSQ VDDQ I/O9 I/O8 VSS NC VDD ZZ(2) I/O7 I/O6 VDDQ VSSQ I/O5 I/O4 I/O3 I/O2 VSSQ VDDQ I/O1 I/O0 NC
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 NC
3780 drw 02
.
Top View TQFP
NOTES 1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is VIL. 2. Pin 64 can be left unconnected and the device will always remain in active mode.
5 6.42
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1, 2)
Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. ZZ = LOW for this table. 3. OE is an asynchronous input.
Address Used None None None None None External External External External External External External Next Next Next Next Next Next Next Next Next Next Next Next Current Current Current Current Current Current Current Current Current Current Current Current
CE H L L L L L L L L L L L X X X X H H H H X X H H X X X X H H H H X X H H
CS0 X X L X L H H H H H H H X X X X X X X X X X X X X X X X X X X X X X X X
CS1 X H X H X L L L L L L L X X X X X X X X X X X X X X X X X X X X X X X X
ADSP X L L X X L L H H H H H H H H H X X X X H H X X H H H H X X X X H H X X
ADSC L X X L L X X L L L L L H H H H H H H H H H H H H H H H H H H H H H H H
ADV X X X X X X X X X X X X L L L L L L L L L L L L H H H H H H H H H H H H
GW X X X X X X X H H H H L H H H H H H H H H L H L H H H H H H H H H L H L
BWE X X X X X X X H L L L X H H X X H H X X L X L X H H X X H H X X L X L X
BWX X X X X X X X X H H L X X X H H X X H H L X L X X X H H X X H H L X L X
OE (3) X X X X X L H L L H X X L H L H L H L H X X X X L H L H L H L H X X X X
CLK
I/O Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DOUT Hi-Z DOUT DOUT Hi-Z DIN DIN DOUT Hi-Z DOUT Hi-Z DOUT Hi-Z DOUT Hi-Z DIN DIN DIN DIN DOUT Hi-Z DOUT Hi-Z DOUT Hi-Z DOUT Hi-Z DIN DIN DIN DIN
3780 tbl 07
6
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1)
Operation Read Read Write all Bytes Write all Bytes Write Byte 1 Write Byte 2 Write Byte 3 Write Byte 4
(2) (2) (2) (2)
GW H H L H H H H H
BWE H L X L L L L L
BW1 X H X L L H H H
BW2 X H X L H L H H
BW3 X H X L H H L H
BW4 X H X L H H H L
3780 tbl 08
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table(1)
Operation Read Read Write Deselected Sleep Mode OE L H X X X ZZ L L L L H I/O Status Data Out (I/O0-I/O31) High-Z High-Z -- Data In (I/O0-I/O31) High-Z High-Z Power Active Active Active Standby Sleep
3780 tbl 09
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1 A1 First Address Second Address Third Address Fourth Address(1) 0 0 1 1 A0 0 1 0 1 Sequence 2 A1 0 0 1 1 A0 1 0 1 0 Sequence 3 A1 1 1 0 0 A0 0 1 0 1 Sequence 4 A1 1 1 0 0 A0 1 0 1 0
3780 tbl 10
NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1 A1 First Address Second Address Third Address Fourth Address
(1)
Sequence 2 A1 0 1 1 0 A0 1 0 1 0
Sequence 3 A1 1 1 0 0 A0 0 1 0 1
Sequence 4 A1 1 0 0 1 A0 1 0 1 0
3780 tbl 11
A0 0 1 0 1
0 0 1 1
NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state.
7 6.42
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V +10/-5%)
Symbol |ILI| |ILI| |ILO| VOL VOH Parameter Input Leakage Current ZZ & LBO Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage
(1)
Test Conditions VDD = Max., VIN = 0V to VDD VDD = Max., VIN = 0V to VDD CE > VIH or OE > VIH, VOUT = 0V to VDD, VDD = Max. IOL = 5mA, VDD = Min. IOH = -5mA, VDD = Min.
Min.
___ ___
Max. 5 30 5 0.4
___
Unit A A A V V
___ ___
2.4
3780 tbl 12 NOTE: 1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VHD = VDDQ0.2V, VLD = 0.2V)
IDT71V633S11(3) Symbol IDD ISB ISB1 IZZ Parameter Operating Core Power Supply Current Standby Core Power Supply Current Full Standby Core Power Supply Current Full Sleep Mode Core Power Supply Current Test Conditions Device Selected, Outputs Open, VDD = Max., VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2) Device Deselected, Outputs Open, VDD = Max., VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2) Device Deselected, Outputs Open, VDD = Max., VDDQ = Max., VIN > VHD or < VLD, f = 0(2) ZZ > VHD, VDD = Max. Com'l 160 45 15 15 Ind'l -- -- -- -- IDT71V633S12 Com'l 150 40 15 15 Ind'l 150 40 15 15 Unit mA mA mA mA
3780 tbl 13
NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing. 3. 0C to +70C temperature range only.
AC Test Loads
VDDQ/2
+3.3V 317
DATA OUT
50
DATA OUT
Z0 = 50
3780 drw 03
351
5pF*
Figure 1. AC Test Load
6 5 4 3 tCD (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200
3780 drw 05
3780 drw 04
* Including scope and jig capacitance.
Figure 2. High-Impedence Test Load
(for tOHZ, tCHZ, tOLZ, and tDC1)
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC Test Load 0 to 3.0V 2ns 1.5V 1.5V See Figures 1 and 2
3780 tbl 14
Figure 3. Lumped Capacitive Load, Typical Derating 8
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
71V633S11(5) Symbol Clock Parameters tCYC tCH tCL
(1)
71V633S12 Min. Max. Unit
Parameter
Min.
Max.
Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width
20 6 6
____ ____ ____
20 6 6
____ ____ ____
ns ns ns
(1)
Output Parameters tCD tCDC tCLZ
(2) (2)
Clock High to Valid Data Clock High to Data Change Clock High to Output Active Clock High to Data High-Z Output Enable Access Time Output Enable Low to Data Active Output Enable High to Data High-Z
____
11
____ ____
____
12
____ ____
ns ns ns ns ns ns ns
3 0 3
____
3 0 3
____
tCHZ tOE
6 4
____
6 4
____
tOLZ(2) tOHZ (2) Setup Times tSA tSS tSD tSW tSAV tSC Hold Times tHA tHS tHD tHW tHAV tHC
0
____
0
____
6
6
Address Setup Time Address Status Setup Time Data in Setup Time Write Setup Time Address Advance Setup Time Chip Enable/Select Setup Time
2.5 2.5 2.5 2.5 2.5 2.5
____ ____ ____ ____ ____ ____
2.5 2.5 2.5 2.5 2.5 2.5
____ ____ ____ ____ ____ ____
ns ns ns ns ns ns
Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Address Advance Hold Time Chip Enable/Select Hold Time
0.5 0.5 0.5 0.5 0.5 0.5
____ ____ ____ ____ ____ ____
0.5 0.5 0.5 0.5 0.5 0.5
____ ____ ____ ____ ____ ____
ns ns ns ns ns ns
Sleep Mode and Configuration Parameters tZZPW tZZR(3) tCFG
(4)
ZZ Pulse Width ZZ Recovery Time Configuration Set-up Time
100 100 80
____ ____ ____
100 100 80
____ ____ ____
ns ns ns
3780 tbl 15
NOTES: 1. Measured as HIGH above 2.0V and LOW below 0.8V. 2. Transition is measured 200mV from steady-state. 3. Device must be deselected when powered-up from sleep mode. 4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation. 5. 0C to +70C temperature range only.
9 6.42
tCYC
CLK tCH tCL
tSS tHS
ADSP
(1)
ADSC tHA Ax tSW tHW Ay
tSA
ADDRESS
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
GW, BWE, BWx tHC tSAVtHAV
tSC
CE, CS1
Timing Waveform of Read Cycle(1,2)
(Note 3)
10
ADV inserts a wait-state
ADV
tOE tCD tOHZ tCDC
O1(Ax) O1(Ay) O2(Ay)
OE
tOLZ
(Burst wraps around to its initial state)
tCHZ
O3(Ay) O4(Ay) O1(Ay) O2(Ay)
DATAOUT
Output Disabled Flow-through Read
Burst Flow-through Read
3780 drw 06
Commercial and Industrial Temperature Ranges
NOTES: 1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc., where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
.
tCYC
CLK tCH tCL
(2)
tSS tHS
ADSP
tSA tHA Ax tSW tHW Ay Az
ADDRESS
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
GW
ADV
Timing Waveform of Combined Read and Write Cycles(1,2,3)
11 6.42
OE tSD tHD tOE tCD tCLZ tOHZ O1(Ax) I1(Ay) tCDC tOLZ
DATAIN
DATAOUT
O1(Az)
O2(Az)
O3(Az)
O4(Az)
Single Read
Write
Flow-through Burst Read
3780 drw 07
Commercial and Industrial Temperature Ranges
NOTES: 1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay. O1 (Az) represents the first output from the external address Az; O2 (Az) represents the next output data in the burst sequence of the base address Az, etc., where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
.
tCYC
CLK tCH tCL
tSS tHS
ADSP
(1)
ADSC
tSA tHA Ay
BWE is ignored when ADSP initiates burst
ADDRESS
Ax
Az tHW tSW
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
GW
tSC tHC
CE, CS1 tSAV tHAV
(Note 3)
Timing Waveform of Write Cycle No. 1 GW Controlled(1,2,3)
12
(ADV suspends burst)
ADV
OE tSD I1(Ax) tOHZ I1(Ay) I2(Ay) I2(Ay)
(3)
tHD
DATAIN
I3(Ay)
I4(Ay)
I1(Az)
I2(Az)
I3(Az)
DATAOUT
O3(Aw)
O4(Aw)
3780 drw 08
Commercial and Industrial Temperature Ranges
NOTES: 1. ZZ input is LOW, BWE is HIGH, and LBO is Don't Care for this cycle. 2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc., where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
.
tCYC
CLK tCH tCL
tSS tHS
ADSP
ADSC
tSA tHA Ax
BWE is ignored when ADSP initiates burst
ADDRESS
Ay Az
tHW tSW
BWE
BWx is ignored when ADSP initiates burst
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
tHW tSW
BWx
tSC tHC
CE, CS1 tSAV
Timing Waveform of Write Cycle No. 2 Byte Controlled(1,2,3)
13 6.42
(ADV suspends burst)
(Note 3)
ADV
OE tSD I1(Ax) tOHZ I1(Ay) I2(Ay) I2(Ay) I3(Ay) I4(Ay) I1(Az)
tHD
DATAIN
I2(Az)
I3(Az)
DATAOUT Single Write
O3(Aw)
O4(Aw) Burst Write Extended Burst Write
Burst Read
3780 drw 09
Commercial and Industrial Temperature Ranges
NOTES: 1. ZZ input is LOW, GW is HIGH, and LBO is Don't Care for this cycle. 2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc., where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
.
tCYC
CLK tCH tCL
tSS
tHS
ADSP
ADSC tHA Az
tSA
ADDRESS
Ax
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
GW tHC
tSC
CE, CS1
(Note 4)
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
14
tOE
O1(Ax)
ADV
OE
tOLZ
DATAOUT
tZZR tZZPW Single Read Snooze Mode
3780 drw 10
ZZ
Commercial and Industrial Temperature Ranges
NOTES: 1. Device must power up in deselected mode. 2. LBO input is Don't Care for this cycle. 3. It is not necessary to retain the state of the input registers throughout the Power-down cycle. 4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
.
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW, BWE, BWx
CE, CS1
CS0
OE
DATAOUT
(Av)
(Aw)
(Ax)
(Ay)
3780 drw 11
.
NOTES: 1 ZZ input is LOW, ADV is HIGH, and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. 3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
15 6.42
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW
CE, CS1
CS0
DATAIN
(Av)
(Aw)
(Ax)
(Ay)
(Az)
3780 drw 12
.
NOTES: 1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. 3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW. 4. For write cycles, ADSP and ADSC have different limitations.
16
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
100-pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
17 6.42
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71V633 Device Type S Power X Speed PF Package X Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C)
PF
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
.
11* 12
tCD in nanoseconds
* Commercial only.
PART NUMBER
71V633S11PF 71V633S12PF
SPEED IN MEGAHERTZ
50 MHz 50 MHz
tCD PARAMETER
11 ns 12 ns
CLOCK CYCLE TIME
20 ns 20 ns
3780 drw 13
18
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
9/9/99 Pg. 6-8 Pg. 10-14 Pg. 18 Pg. 1, 4, 8, 9, 17 Pg. 1 Pg. 17 Updated to new format Reordered pages, updated notes Updated notes Added Datasheet Document History Added Industrial temperature range offering Corrected -12 speed Added 100pinTQFP Package Diagram Outline Not recommended for new designs Removed "Not recommended for new designs" from the background on the datasheet
9/30/99 10/8/99 04/04/00 08/09/00 08/17/01
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408 492-8674 www.idt.com
for TECH SUPPORT: sramhelp@idt.com 800 544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
19 6.42

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